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GNU sde-as
for MIPS architectures supports several
different MIPS processors, and a range of MIPS ISA levels. For
information about the MIPS instruction set, and an overview of
MIPS assembly conventions, view the list of publications in the
development tools section of
MIPS Technologies'
website.
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The MIPS configurations of GNU sde-as
support these
special options:
-G num
gp
register. Set to zero to disable this
optimization.
The default value is 8, unless generating position-independent code, in which
case it is 0, because the gp
register is then used for other purposes.
-O
-Onum
nop
instructions, and will fill a branch
delay slot with the instruction immediately before the branch, if that
is safe to do. You can disable the branch delay slot filling only by
specifying `-O0'.
-EB
-EL
-mcpu=cpu
nop
instructions as required for different CPUs.
The list of recognised CPU is as follows, grouped with aliases on the same line:
r2000, r2k, r3000, r3k, r6000, r6k, r4000, r4400, r4200, r4310, r4300, r4111, r4100, orion, r4600, r4700, r4640, r4650, r8000, r8k, rc32364, rc3236x, cronus, r5000, r5k, r5400, r5432, r5464, r54xx, r5500, r55xx rc64574, rc64575, rc6457x, r10000, r12000, r10k, r12k, 4kc, 4kp, 4km, 4kec, 4kep, 4kem, 4ksc, 4ksd. m4k, 5kc, 5kf, 24kc, 24kf, 20kc, 25kf, rm5230, rm5231, rm5260, rm5261, rm5270, rm5271, rm52xx, rm7000, rm7k, r1900, pr1900, r3900, pr3900 tx39, r4900, tx49, lr33000, lr33k, 4001, tr4101, tr4102, tr410x, cw4001, cw4002, cw400x 4010, cw4010, cw401x atm2, atmizer2, apu, 4020, cw4020 |
-mips1
-mips2
-mips3
-mips4
-mips5
-mips32
-mips32r2
-mips64
-mips64r2
-mips16
This flag is actually ignored by the assembler, which always starts off using the conventional MIPS instruction set. It is difficult and usually pointless to try to write assembler code for MIPS16--if you really need to then you can mix MIPS16 and conventional MIPS code using explicit `.set mips16' and `.set nomips16' directives.
MIPS16 CPUs can be either 32-bit or 64-bit implementations. To compile for a 64-bit MIPS16 CPU you should first specify a 64-bit base ISA, e.g. `-mips3'.
-mips16e
Like `-mips16', the `-mips16e' command line option does not cause MIPS16e code to be generated--that still needs a `.set mips16' directive in the code. But specifying `-mips16e' with no other ISA flag will cause MIPS32 to be selected as the 32-bit ISA.
To generate 64-bit MIPS16e code, first specify a 64-bit base ISA, e.g. `-mips64'.
-msmartmips
-mips3D
-mabi=32
-mabi=o64
-mabi=n32
-mabi=64
-mabi=eabi
-mabi=meabi
-mgp32
-mgp64
-mfp32
-mfp64
-mhard-float
-msingle-float
-msoft-float
-mno-float
-mno-div-checks
-mdiv-checks
--trap
--no-break
sde-as
automatically macro expands certain division and
multiplication instructions to check for overflow and division by zero. This
option causes sde-as
to generate code to take a trap exception
rather than a break exception when an error is detected. The trap instructions
are only supported at Instruction Set Architecture level 2 and higher.
--break
--no-trap
-KPIC
-call_shared
-xgot
-non_shared
-membedded-pic
-membedded-data
-mno-gpconst
.lit4
or .lit8
data sections.
-mno-fix-cw4010
nop
before any branch which is itself a branch target.
This workaround is enabled automatically if either no CPU is selected and the
ISA is MIPS II or lower, or if the r3000, cw4010 or atm2 CPU type is selected.
-mno-fix-vr4300
nop
between a floating-point multiply and an immediately
following integer or floating-point multiply. This workaround is enabled
automatically if either no CPU is selected and the ISA is MIPS III or lower,
or if the r3000, r4000 or Vr4300 CPU type is selected.
-mno-fix-r4000
nop
between a variable shift instruction and a multiply or
divide. This workaround is enabled automatically if either no CPU is selected
and the ISA is MIPS III or lower, or if the r3000 or r4000 CPU type is
selected.
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Assembling for a MIPS ECOFF or ELF target supports some
additional sections besides the usual `.text', `.data' and
.bss
. The additional sections are `.rdata', used for
read-only data, `.sdata', used for small data, and `.sbss',
used for small common objects. In the case of ELF the read-only
data section is called `.rodata'.
When assembling for ECOFF or ELF, the assembler uses the
$gp
($28
) register to form the address of "small data.
Any symbol in the .sdata
or .sbss
sections is considered
"small" in this sense. For external objects, or for objects in the
.bss
section, you can use the sde-gcc
`-G' option
to control the size of objects addressed via $gp
; the default
value is 8, meaning that a reference to any object eight bytes or
smaller uses $gp
. Passing `-G 0' to sde-as
prevents it from using the $gp
register on the basis of object
size (but the assembler uses $gp
for objects in .sdata
or
sbss
in any case). The size of an object in the .bss
section is set by the .comm
or .lcomm
directive that
defines it. The size of an external object may be set with the
.extern
directive. For example, `.extern sym,4' declares
that the object at sym
is 4 bytes in length, while leaving
sym
otherwise undefined.
Using small data requires linker support, and assumes that the
$gp
register is correctly initialized (normally done automatically by
the startup code). MIPS assembly code must not modify the
$gp
register.
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MIPS ELF sde-as
supports several directives used
for generating debugging information which are not supported by
traditional MIPS assemblers. These are .stabd
,
.stabn
, and .stabs
.
The debugging information generated by the three
.stab
directives can only be read by GDB, not by traditional
MIPS debuggers (this enhancement is required to fully support C++
debugging). These directives are primarily used by compilers, not
assembly language programmers!
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GNU sde-as
supports an additional directive to change
the MIPS Instruction Set Architecture level on the fly: .set
mipsn
. n should be a number from 0 to 5, 32 or 64. A
non-zero value makes the assembler accept instructions for the
corresponding ISA level, from that point on in the assembly.
.set mipsn
affects not only which instructions are
permitted, but also how certain macros are expanded. The `.set
mips0' directive restores the ISA level to its original level:
either the level you selected with command line options, or the default
for your configuration. You can use this feature to permit specific 64
bit instructions while assembling with a 32 bit ISA. Use this directive
with care!
The `.set gp64' directive affects how immediate values and certain MIPS macro instructions are expanded, so that 64-bit values will be held in a single register. This is only valid if a 64 bit ISA has already been selected. The `.set gp32' directive has the opposite effect, and the `.set nogp64' or `.set nogp32' directives return to the level selected by the command line options.
The `.set fp64' directive tells the assembler to assume the existence of 32 64-bit floating-point registers. This is only valid if a 64 bit ISA has already been selected. The `.set fp32' directive has the opposite effect, and the `.set nofp64' or `.set nofp32' directives return to the level selected by the command line options.
The directive `.set mips16' puts the assembler into MIPS16 mode, in which it will generate the compressed instruction set. Use `.set nomips16' to return to normal 32 bit mode. The directive `.set mips16e' is similar, but enables the extended MIPS16e instruction set.
The `.set smartmips' directive enables use of the SmartMIPS extensions to the MIPS32 ISA; the `.set nosmartmips' directive reverses that.
Traditional MIPS assemblers do not support these directives.
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By default, MIPS16 instructions are automatically extended to 32 bits when necessary. The directive `.set noautoextend' will turn this off. When `.set noautoextend' is in effect, any 32 bit instruction must be explicitly extended with the `.e' modifier (e.g., `li.e $4,1000'). The directive `.set autoextend' may be used to once again automatically extend instructions when necessary.
This directive is only meaningful when in MIPS16 mode. Traditional MIPS assemblers do not support this directive.
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The .insn
directive tells sde-as
that the following
data is actually instructions. This makes a difference in MIPS16 mode:
when loading the address of a label which precedes instructions,
sde-as
automatically adds 1 to the value, so that jumping to
the loaded address will do the right thing.
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The directives .set push
and .set pop
may be used to save
and restore the current settings for all the options which are
controlled by .set
. The .set push
directive saves the
current settings on a stack. The .set pop
directive pops the
stack and restores the settings.
These directives can be useful inside an macro which must change an option such as the ISA level or instruction reordering but does not want to change the state of the code which invoked the macro.
Traditional MIPS assemblers do not support these directives.
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