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8. MIPS Dependent Features

GNU sde-as for MIPS architectures supports several different MIPS processors, and a range of MIPS ISA levels. For information about the MIPS instruction set, and an overview of MIPS assembly conventions, view the list of publications in the development tools section of MIPS Technologies' website.

8.1 Assembler options  
8.2 MIPS object code  
8.3 Directives for debugging information  
8.4 Directives to override the ISA level  
8.5 Directives for extending MIPS16 instructions  
8.6 Directive to mark data as an instruction  
8.7 Directives to save and restore options  


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8.1 Assembler options

The MIPS configurations of GNU sde-as support these special options:

-G num
This option sets the largest size of an object that can be referenced implicitly with the gp register. Set to zero to disable this optimization. The default value is 8, unless generating position-independent code, in which case it is 0, because the gp register is then used for other purposes.

-O
-Onum
Selects the assembler optimization level. By default the assembler will try to avoid inserting nop instructions, and will fill a branch delay slot with the instruction immediately before the branch, if that is safe to do. You can disable the branch delay slot filling only by specifying `-O0'.

-EB
-EL
Use `-EB' to select big-endian output, and `-EL' for little-endian.

-mcpu=cpu
Generate code for a particular MIPS CPU. This option enables use of any extra instructions specific to each CPU, and enables or disables insertion of nop instructions as required for different CPUs.

The list of recognised CPU is as follows, grouped with aliases on the same line:

 
r2000, r2k,
r3000, r3k,
r6000, r6k,
r4000, r4400, r4200,
r4310, r4300,
r4111, r4100,
orion, r4600, r4700,
r4640, r4650,
r8000, r8k,
rc32364, rc3236x, cronus,
r5000, r5k,
r5400, r5432, r5464, r54xx,
r5500, r55xx
rc64574, rc64575, rc6457x,
r10000, r12000, r10k, r12k,
4kc, 4kp, 4km, 4kec, 4kep, 4kem, 4ksc, 4ksd. m4k,
5kc, 5kf, 
24kc, 24kf,
20kc, 25kf,
rm5230, rm5231, rm5260, rm5261,
rm5270, rm5271, rm52xx,
rm7000, rm7k,
r1900, pr1900, r3900, pr3900 tx39,
r4900, tx49,
lr33000, lr33k,
4001, tr4101, tr4102, tr410x,
cw4001, cw4002, cw400x
4010, cw4010, cw401x
atm2, atmizer2, apu,
4020, cw4020

-mips1
-mips2
-mips3
-mips4
-mips5
-mips32
-mips32r2
-mips64
-mips64r2
Generate code for a particular MIPS Instruction Set Architecture level. You can also switch instruction sets during the assembly; see Directives to override the ISA level.

-mips16
MIPS16 is an instruction set extension which provides a subset of true MIPS instructions, with a restricted set of registers, and coded as 16-bit instructions. It can make for much smaller program binaries. CPUs supporting MIPS16 switch from interpreting conventional MIPS to MIPS16 instructions when they are asked to fetch an instruction from an odd address.

This flag is actually ignored by the assembler, which always starts off using the conventional MIPS instruction set. It is difficult and usually pointless to try to write assembler code for MIPS16--if you really need to then you can mix MIPS16 and conventional MIPS code using explicit `.set mips16' and `.set nomips16' directives.

MIPS16 CPUs can be either 32-bit or 64-bit implementations. To compile for a 64-bit MIPS16 CPU you should first specify a 64-bit base ISA, e.g. `-mips3'.

-mips16e
MIPS16e is an enhancement of the MIPS16 instruction set, which provides even greater code size reductions. It is only ever available when combined with a MIPS32 or MIPS64 compliant.

Like `-mips16', the `-mips16e' command line option does not cause MIPS16e code to be generated--that still needs a `.set mips16' directive in the code. But specifying `-mips16e' with no other ISA flag will cause MIPS32 to be selected as the 32-bit ISA.

To generate 64-bit MIPS16e code, first specify a 64-bit base ISA, e.g. `-mips64'.

-msmartmips
Enables the SmartMIPS extensions to the MIPS32 instruction set, which provides a number of new instructions which target smartcard and cryptographic applications.

-mips3D
MIPS-3D is an extension to the MIPS64 instruction set, which provides a paired single floating-point vector type, and a number of new floating-point instructions which target geometry processing.

-mabi=32
-mabi=o64
-mabi=n32
-mabi=64
-mabi=eabi
-mabi=meabi
Generate code for the indicated ABI. At the moment, the only effect of this option is that `-mabi=n64' will select 64-bit ELF object code format and address computations; the other ABI modes have no effect on the assembler.

-mgp32
Assume that the 32 general purpose registers are 32 bits wide. This is the default when a 32-bit ISA is specified or implied. Such code will run correctly on 64-bit MIPS CPUs so long as every function which might call your code is built the same way. This option affects how some macro instructions are expanded, but you may also want to generate 32-bit code while other enhanced features of the 64-bit ISAs. Also, some 32-bit OSes only save the 32-bit registers on a context switch, so it is essential never to use the 64-bit registers.

-mgp64
Assume that the 32 general purpose registers are 64 bits wide. This is the default when a 64-bit ISA is specified or implied, and illegal unless your CPU implements a 64-bit instruction set; so it's hard to see when you'd use this option explicitly, but is provided in the interests of symmetry with `-mgp32'.

-mfp32
Assume that 32 32-bit floating point registers are available, but only the even-numbered 16 are used for arithmetic (the odd-numbered registers are used quietly by the assembler for loading/storing the high-order bits of double-precision values). This is the default when a 32-bit ISA is specified or implied.

-mfp64
Assume that 32 64-bit floating point registers are available. This is the default when a 64-bit ISA is specified or implied, and indeed it is usually usually illegal with 32-bit ISAs. The exception is that it can be used with `-mips32r2', since MIPS32 release 2 adds new instructions which allow a 32-bit CPU to be combined with a 64-bit FPU.

-mhard-float
Enable use of the floating-point coprocessor instructions. This is the default.

-msingle-float
Enable use of the floating-point coprocessor instructions, but only for single-precision arithmetic (as implemented on the r4640 and r4650). Any use of double-precision arithmetic will cause the assembler to generate an error message.

-msoft-float
-mno-float
These two options are equivalent, and will cause the assembler to generate an error message if any floating-point instructions are used.

-mno-div-checks
-mdiv-checks
Disable (or enable) the automatic generation of code to check for division by zero, or divide overflow.

--trap
--no-break
sde-as automatically macro expands certain division and multiplication instructions to check for overflow and division by zero. This option causes sde-as to generate code to take a trap exception rather than a break exception when an error is detected. The trap instructions are only supported at Instruction Set Architecture level 2 and higher.

--break
--no-trap
Generate code to take a break exception rather than a trap exception when an divide or multiply overflow is detected. This is the default.

-KPIC
-call_shared
These options both enable the generation of MIPS/abi position-independent code, as used on many modern Unix systems. This can also be enabled by using the `.abicalls' pseudo-op.

-xgot
When generating MIPS/abi code, assume a "large" global offset table (more than 32K global symbols). This generates a longer sequence of instructions for each GOT reference.

-non_shared
Disable generation of position-independent code. This is the default.

-membedded-pic
Generate PIC code suitable for some embedded systems. All calls are made using PC relative address, and all data is addressed using the gp register. No more than 65536 bytes of global data may be used. This currently only works on targets which use ECOFF; it does not work with ELF. Since MIPS SDE uses ELF as its object format, this feature is not supported.

-membedded-data
-mno-gpconst
These equivalent options cause any floating-point immediate values to be placed in the read-only data section, rather than the .lit4 or .lit8 data sections.

-mno-fix-cw4010
Disables an assembler workaround for early versions of the LSI CW4010 CPU, which inserts a nop before any branch which is itself a branch target. This workaround is enabled automatically if either no CPU is selected and the ISA is MIPS II or lower, or if the r3000, cw4010 or atm2 CPU type is selected.

-mno-fix-vr4300
Disables an assembler workaround for early versions of the Vr4300 CPU, which inserts a nop between a floating-point multiply and an immediately following integer or floating-point multiply. This workaround is enabled automatically if either no CPU is selected and the ISA is MIPS III or lower, or if the r3000, r4000 or Vr4300 CPU type is selected.

-mno-fix-r4000
Disables an assembler workaround for early versions of the R4000, which inserts a nop between a variable shift instruction and a multiply or divide. This workaround is enabled automatically if either no CPU is selected and the ISA is MIPS III or lower, or if the r3000 or r4000 CPU type is selected.


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8.2 MIPS object code

Assembling for a MIPS ECOFF or ELF target supports some additional sections besides the usual `.text', `.data' and .bss. The additional sections are `.rdata', used for read-only data, `.sdata', used for small data, and `.sbss', used for small common objects. In the case of ELF the read-only data section is called `.rodata'.

When assembling for ECOFF or ELF, the assembler uses the $gp ($28) register to form the address of "small data. Any symbol in the .sdata or .sbss sections is considered "small" in this sense. For external objects, or for objects in the .bss section, you can use the sde-gcc `-G' option to control the size of objects addressed via $gp; the default value is 8, meaning that a reference to any object eight bytes or smaller uses $gp. Passing `-G 0' to sde-as prevents it from using the $gp register on the basis of object size (but the assembler uses $gp for objects in .sdata or sbss in any case). The size of an object in the .bss section is set by the .comm or .lcomm directive that defines it. The size of an external object may be set with the .extern directive. For example, `.extern sym,4' declares that the object at sym is 4 bytes in length, while leaving sym otherwise undefined.

Using small data requires linker support, and assumes that the $gp register is correctly initialized (normally done automatically by the startup code). MIPS assembly code must not modify the $gp register.


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8.3 Directives for debugging information

MIPS ELF sde-as supports several directives used for generating debugging information which are not supported by traditional MIPS assemblers. These are .stabd, .stabn, and .stabs.

The debugging information generated by the three .stab directives can only be read by GDB, not by traditional MIPS debuggers (this enhancement is required to fully support C++ debugging). These directives are primarily used by compilers, not assembly language programmers!


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8.4 Directives to override the ISA level

GNU sde-as supports an additional directive to change the MIPS Instruction Set Architecture level on the fly: .set mipsn. n should be a number from 0 to 5, 32 or 64. A non-zero value makes the assembler accept instructions for the corresponding ISA level, from that point on in the assembly. .set mipsn affects not only which instructions are permitted, but also how certain macros are expanded. The `.set mips0' directive restores the ISA level to its original level: either the level you selected with command line options, or the default for your configuration. You can use this feature to permit specific 64 bit instructions while assembling with a 32 bit ISA. Use this directive with care!

The `.set gp64' directive affects how immediate values and certain MIPS macro instructions are expanded, so that 64-bit values will be held in a single register. This is only valid if a 64 bit ISA has already been selected. The `.set gp32' directive has the opposite effect, and the `.set nogp64' or `.set nogp32' directives return to the level selected by the command line options.

The `.set fp64' directive tells the assembler to assume the existence of 32 64-bit floating-point registers. This is only valid if a 64 bit ISA has already been selected. The `.set fp32' directive has the opposite effect, and the `.set nofp64' or `.set nofp32' directives return to the level selected by the command line options.

The directive `.set mips16' puts the assembler into MIPS16 mode, in which it will generate the compressed instruction set. Use `.set nomips16' to return to normal 32 bit mode. The directive `.set mips16e' is similar, but enables the extended MIPS16e instruction set.

The `.set smartmips' directive enables use of the SmartMIPS extensions to the MIPS32 ISA; the `.set nosmartmips' directive reverses that.

Traditional MIPS assemblers do not support these directives.


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8.5 Directives for extending MIPS16 instructions

By default, MIPS16 instructions are automatically extended to 32 bits when necessary. The directive `.set noautoextend' will turn this off. When `.set noautoextend' is in effect, any 32 bit instruction must be explicitly extended with the `.e' modifier (e.g., `li.e $4,1000'). The directive `.set autoextend' may be used to once again automatically extend instructions when necessary.

This directive is only meaningful when in MIPS16 mode. Traditional MIPS assemblers do not support this directive.


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8.6 Directive to mark data as an instruction

The .insn directive tells sde-as that the following data is actually instructions. This makes a difference in MIPS16 mode: when loading the address of a label which precedes instructions, sde-as automatically adds 1 to the value, so that jumping to the loaded address will do the right thing.


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8.7 Directives to save and restore options

The directives .set push and .set pop may be used to save and restore the current settings for all the options which are controlled by .set. The .set push directive saves the current settings on a stack. The .set pop directive pops the stack and restores the settings.

These directives can be useful inside an macro which must change an option such as the ISA level or instruction reordering but does not want to change the state of the code which invoked the macro.

Traditional MIPS assemblers do not support these directives.


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